The present invention relates to manufacture of semiconductor integrated circuits and, more particularly, to lithographic techniques for increasing available product space on a semiconductor wafer.
Semiconductor integrated circuits are commonly built on a wafer or substrate by deposition of conductive layers separated by non-conductive layers with each conductive layer being patterned to establish desired conductive paths or traces. The patterns of traces are often defined by photolithographic processes in which a radiation sensitive or photo-resist layer is spread over the conductive layer and exposed to appropriate radiation—light, UV, x-ray, for example—through a patterned mask formed on a reticle.
Each wafer is typically physically larger than an integrated circuit being created and is therefore dividable into multiple areas or dies with each die forming a single integrated circuit. Generally, each integrated circuit formed on a wafer is identical, i.e., all SRAM or all DRAM or some other type circuit. However, it is also common to form test circuits on the wafer in order to verify that the circuit forming process is proceeding properly.
One process of circuit formation uses reticles having multiple images so that multiple dies are concurrently exposed. A stepper is used to accurately position the reticle with respect to the wafer for each succeeding exposure. With this process, a different reticle is required for each layer forming the integrated circuit. Another process uses a reticle with multiple images in which each image corresponds to a layer or level of circuit formation. In this latter process, only one circuit is exposed at a time with the remaining images being blocked by shutters. Such a process is described in U.S. Pat. No. 6,040,892. Both of these processes use multiple images on a single reticle to address the high cost of multiple, complex reticles.
There is a further problem not addressed by the above described processes in that the multiple images typically include images for forming test circuits. The test circuits are larger than the product circuits and consume substantial space on each wafer, particularly since each exposure of a reticle produces another test circuit. Reducing the number of test circuits would therefore produce higher product yield per wafer and reduce manufacturing cost.